1. Field of the Invention
This invention generally relates to improved processing techniques for the production of semiconductor devices, and, more particularly, to a method of fabricating semiconductor transistors whereby the glass deposition and driving steps normally preceding the creation of diffused emitter sites are eliminated.
2. Prior Art
In the manufacture of semiconductor devices and integrated circuits, the standard method of processing locked geometry type transistors such as diffused junction transistors, involves a substantial number of steps, for example, a 12 step process prior to metallization is not uncommon. The old method has the disadvantage of longer cycle times and requires a significant number of heating and photoresist steps which may adversly affect production yields.
The use of diffused junction transistors is well known in the art. Generally these devices are formed by junction between semiconductor layers each having a conductivity type which is reverse to the other, i.e., by a P-N junction. These devices have been traditionally produced by introducing a donor or acceptor impurity into the semiconductor substrate by means of known diffusion techniques. In the diffusion technique, after a window is formed in a masking layer provided on the surface of the semiconductor substrate, an impurity, such as, for example, phosphorous, arsenic, boron and the like is introduced from a vapor phase or a solid phase. The impurity diffuses into the semiconductor and forms an active region.
The construction of a semiconductor element prepared by selectively diffusing an impurity through a mask consisting of an insulating coating or film by a process as mentioned hereinabove, is known as "planar structure." To form this planar structure, a mask comprising an insulating layer having openings or windows which terminate at the surface of a semiconductor is used to diffuse the impurity of different conductivity type from that of the semiconductor substrate. This forms the base region in the substrate. Thereafter, a second insulating layer is formed to cover said windows, and a second set of windows are formed to diffuse therethrough another impurity having a different conductivity type from the base region to form the emitter regions. The windows through the insulating layer covering the semiconductor surface, are typically formed by well known photo-etching techinques.
In forming the second set of windows through the insulating layer in the prior art method, it is necessary to closely control the positions thereof, and it is generally accepted that as the number of process steps required to form these windows through the insulating film is increased, the difficulty of closely controlling the positions of the perforations will be increased. Thus, for example, to prepare transistors of double diffusion type, a total of the three photo-etching steps are generally required. This process is known as "mask aligning operation" because it includes a step of aligning a pattern on the mask with a pattern formed on the semiconductor wafer by manipulating a photographic negative. Thus, the prior art required three basic mask aligning operations. In order to prepare high frequency micro wave diffused transistors, these mask aligning operations must be carried out with an accuracy of from 0.25 to 1.00 microns. And since an increase in the number of mask aligning operations results in an increase in the probability of deviation between the mask pattern and the pattern on the semiconductor substrate, the number of satisfactory transistors formed on a single wafer, is usually reduced, thus decreasing the yield of satisfactory products. It is also to be noted that extremely high quality and expensive apparatus are required to perform such mask aligning operations with high accuracy. Moreover, there are many engineering problems to be solved. for example, the masks themselves are expensive and the mask aligning operations require much time.
More specifically, a conventional 12 step method for manufacturing a locked geometry type transistor is shown in FIG. 1 and will be briefly described. As a first step, a silicon oxide layer having an opening in a predetermined area on one flat face of a P or N-type silicon single crystal is formed and a base region of opposite polarity, for example, a P-type region is created by selectively diffusing a P-type impurity through the opening. Thereafter, a second layer of silicon dioxide is formed on the N-type base region, and additional openings are again disposed therethrough by removing a predetermined protion of the silicon dioxide. A P+ glass is then deposited through the latter openings to form a contact area on the silicon substrate in the base region. An additional passivation coating is next deposited over the P+ glass, and the base drive and P+ drive are completed by heating the wafer in a furnace. Thereafter, N-type emitter regions are defined through the passivation layer utilizing known photo-etch and diffusion techniques. Then another photomasking operation is required to define the base contact regions. Finally, metal interconnects are defined through etched windows so as to be in contact with the desired emitters and P+ regions.
Such conventional methods thus requires more than 10 steps to metallization. In addition, the method requires longer cycle times and various heating and photoresist steps that can lower yields. For example, typical temperature ranges and time periods for processing microwave semiconductors in the aforementioned base diffusion step are approximately 900.degree. to 1125.degree.C for 1/4 to 2 hours.
To overcome this long processing technique, the prior art has disclosed a number of semiconductor fabrication methods. However, the disclosed methods have attacked the problem by improving the masking processes, the fabrication techiques of the masks, and in the design of transistor circuit structures themselves. But the prior art has not significantly reduced the number of processing steps. For example, Lawrence et al., U.S. Pat. No. 3,670,403, disclose a three resist-masking step process for producing field effect transistors. The process includes the steps of depositing on a silicon wafer, sequential layers of protective oxide, silicon nitride, and field oxide followed by the first masking step forming the source and drain regions. Next, an activator impurity and glass are deposited and the second masking step takes place defining contact holes and gate openings using the silicon nitride as an etch stop. Finally the third mask delineates the contact metallization. While this process is disclosed as lowering costs, alignment of each of the masks is difficult and time consuming, and the number of steps is still significant.
In another prior art process disclosed by Tauchi et al., U.S. Pat. No. 3,707,410 another method of manufacturing semiconductor devices is disclosed. This method includes the steps of introducing a first impurity through a mask into a substrate to form a first doped area, followed by a second impurity with a diffusion constant which is greater than that of the first impurity. The problem with such a process is that inasmuch as it is difficult to control the depth an impurity will penetrate into the substrate during a heating step, a double diffusion process compounds an already difficult procedure.
Another prior art process disclosed by Harding et al., U.S. Pat. No. 3,266,127, also points up the problem of multiplicity of steps involving great accuracy and/or heating. In the Harding et al. method of forming contacts on semiconductors, first an interconnection metal is deposited in a desired pattern on an oxide coated semiconductor. A contact area is etched through a portion of the interconnection and through the oxide coating to the surface of the semiconductor. This is followed by selectively depositing an aluminum omic contact in the etched area so as to cover the oxide-free semiconductor surface including an area somewhat larger in size than the etched area. Finally the semiconductor is heated to a temperature sufficient to cause alloying of the contact with the oxide-free surface of the semiconductor.
Even those improved prior art methods such as disclosed by Preece, U.S. Pat. No. 3,585,089 which do attack the problem of the great number of difficult processing steps, have only been able to reduce the number to approximately nine. In Preece, PN junctions are formed by well known techniques such as oxide masking and impurity diffusion. Next a silicon nitride layer is deposited followed by the etching of contact windows. While Preece may reduce the number of steps, the specific steps involved are those requiring a high degree of accuracy and those likely to result in poor reliability, namely, heating the wafer to high temperatures. Thus, while Preece does alleviate the time problem associated with a 12-step process, the process still includes steps which adversely affect production yields.
The present invention is directed towards a method to increase yields and improve the reliability of junction transistor devices and diodes. The present invention is more direct and less costly because fewer steps are necessary to produce locked geometry type transistors. Further, inasmuch as the steps are relatively straight forward, not requiring exacting techniques, the devices thus produced are more reliable.